Senior DFT Technical Manager (San Jose)
We are seeking an experienced Senior DFT Technical Manager to lead DFT design and implementation for advanced SoC products while serving as a key technical interface between customers and MediaTek engineering teams. The ideal candidate will have strong hands‑on experience in pre‑silicon DFT architecture, scan insertion, ATPG, MBIST/LBIST, test coverage closure, DFT verification, silicon bring‑up, diagnosis, and production issue resolution. In this role, you will drive customer‑facing technical engagements from DFT planning, design‑in, implementation, and tape‑out readiness through silicon bring‑up, qualification, yield improvement, and mass‑production ramp. You will work closely with customers and cross‑functional MediaTek teams to define DFT requirements, review implementation quality, resolve complex technical issues, and ensure robust testability from pre‑silicon design through post‑silicon validation. This position requires deep DFT design expertise, strong knowledge of industry EDA tools, excellent customer communication skills, and the ability to drive technical closure across global engineering teams. Responsibilities Lead DFT architecture, planning, implementation review, and tape‑out readiness activities for advanced SoC designs. Serve as the primary technical interface for customers on DFT design, scan architecture, ATPG, MBIST/LBIST, test coverage, DFT verification, silicon bring‑up, diagnosis, ATE correlation, and production‑related issues. Guide customers and internal teams on DFT methodology, implementation flow, coverage closure, pattern generation, DFT signoff, and debug strategy. Review and drive quality of pre‑silicon DFT deliverables, including scan insertion, test compression, MBIST/LBIST integration, boundary scan, ATPG patterns, coverage reports, DFT rule checks, and simulation results. Lead customer technical discussions, design reviews, DFT implementation reviews, issue triage meetings, root‑cause analysis, and corrective‑action planning. Translate customer requirements, design constraints, failure data, logs, waveforms, ATPG reports, diagnosis results, and ATE data into clear debug plans and engineering actions. Drive customer‑reported issues from initial report through reproduction, containment, root‑cause identification, solution validation, and formal closure. Coordinate cross‑functional debugging with DFT, RTL/design, verification, physical design, package, firmware, product engineering, test engineering, and silicon validation teams. Define issue ownership, priority, milestones, escalation paths, and closure criteria for customer‑critical technical issues. Communicate technical findings, risks, workarounds, debug status, and resolution schedules clearly to customers and internal management. Support customer design‑in, DFT signoff, tape‑out readiness, silicon bring‑up, qualification, yield improvement, and mass‑production ramp. Identify gaps in DFT methodology, validation coverage, debug flow, automation, and documentation based on customer feedback and silicon learning. Capture lessons learned and convert them into reusable DFT guidelines, implementation checklists, debug procedures, validation improvements, and best practices. Main Requirements and Qualifications 10 years of experience in semiconductor DFT design, DFT implementation, silicon validation, product engineering, test engineering, application engineering, or customer‑facing technical support. Strong hands‑on knowledge of pre‑silicon DFT methodologies, including scan architecture, scan insertion, test compression, ATPG, MBIST/LBIST, boundary scan, test coverage analysis, DFT rule checking, pattern simulation, and DFT signoff. Familiarity with industry EDA tools such as Synopsys TestMAX/TetraMAX/DFT Compiler and Siemens Tessent, or equivalent DFT/ATPG tool suites. Experience defining and executing DFT implementation flows from RTL/netlist through ATPG pattern generation, coverage closure, simulation, and tape‑out signoff. Hands‑on experience with silicon bring‑up, ATE correlation, production test flow, yield debug, silicon diagnosis, and volume manufacturing support. Proven ability to lead complex technical issue resolution across customers and geographically distributed engineering teams. Strong analytical capability to review DFT reports, coverage reports, DRC results, ATPG logs, pattern simulation results, waveforms, diagnosis data, ATE results, and silicon failure information. Ability to convert incomplete customer or design information into structured DFT implementation actions, debug plans, ownership, milestones, and closure criteria. Excellent customer‑facing communication skills, with the ability to explain complex DFT design, implementation, and silicon issues to both senior technical experts and non‑specialist stakeholders. Strong written and verbal English communication skills. Ability to work effectively across Asia and North America time zones, including occasional off‑hours technical meetings. Strong ownership, urgency, accountability, and follow‑through in customer‑critical situations. Preferred: Experience with HBM, 3DIC, SSN, chiplet‑based products, advanced packaging, logic redundancy design, high‑complexity SoC test methodologies, advanced process‑node products, or large‑scale DFT implementation for complex SoCs. Salary range: $179,000- $286,000 Employee may be eligible for performance bonus, short and long term incentive programs. Actual total compensation will be dependent upon the individual's skills, experience and qualifications. In addition, MediaTek provides a variety of benefits including comprehensive health insurance coverage, life and disability insurance, savings plan, Company paid holidays, Sick Leave, Vacation time, Parental leave, 401K and more. MediaTek is an Equal Opportunity Employer that is committed to inclusion and diversity to all, regardless of age, ancestry, color, disability (mental and physical), exercising the right to family care and medical leave, gender, gender expression, gender identity, genetic information, marital status, medical condition, military or veteran status, national origin, political affiliation, race, religious creed, sex (includes pregnancy, childbirth, breastfeeding and related medical conditions), and sexual orientation. J-18808-Ljbffr
