Staff/Senior Staff GPU Engineer - Shader RTL & Microarchitecture (San Diego)
Position: Staff/Senior Staff GPU Engineer - Shader RTL & Microarchitecture Location: San Diego, CA (4 days onsite) Employment Type: Full-Time Overview In partnership with a top-5 semiconductor company's leadership in SoC design, their GPU IP team is committed to developing industry-leading, feature-rich, and highly PPA-competitive graphics IP. Their GPU technology is deployed across flagship and mainstream mobile SoCs and is also a foundational technology for adjacent markets including laptops, IoT, AI, VR/AR, automotive, and custom ASIC applications. The team is expanding and hiring top GPU talent across multiple disciplines, including architecture, microarchitecture, RTL design, software drivers, compiler technology, performance modeling, power optimization, and silicon validation. Position Summary We are seeking a Staff / Senior Staff GPU Engineer specializing in Shader System RTL Design and Microarchitecture to help define, design, and deliver next-generation GPU IP. The ideal candidate will have strong hands-on experience in GPU shader subsystem microarchitecture, RTL implementation, performance analysis, functional debug, and PPA optimization. In this role, you will drive the design and optimization of GPU shader systems, including shader core pipelines, thread/warp/wave scheduling, instruction dispatch and issue, execution pipelines, register files, operand collection, scoreboard and dependency management, load/store interaction, cache/memory interfaces, synchronization, and cluster-level integration. You will collaborate closely with architecture, compiler, software driver, performance modeling, verification, physical design, and post-silicon teams to deliver best-in-class GPU IP for mobile, automotive, laptop, IoT, AI, VR/AR, and ASIC markets. Key Responsibilities Define, develop, and own GPU shader subsystem microarchitecture specifications. Lead RTL design for shader-related blocks, including shader pipelines, instruction issue, operand collection, register files, dependency tracking, and pipeline control. Collaborate with architecture and compiler teams to translate ISA behavior, API requirements, shader workloads, and performance targets into efficient hardware designs. Analyze GPU workloads and performance data to improve occupancy, throughput, latency hiding, register pressure, and power efficiency. Support the full GPU IP lifecycle, including microarchitecture definition, RTL coding, lint/CDC/RDC cleanup, verification support, synthesis, timing closure, tape-out, bring-up, and post-silicon debug. Partner with verification teams on test plans, coverage, assertions, debug strategies, and directed/random test scenarios. Required Skills & Experience BS, MS, or PhD in Computer Science, Electrical Engineering, Computer Engineering, or related field, or equivalent practical experience. 8 years of experience for Staff level, or 10 years for Senior Staff level, in RTL design, microarchitecture, or architecture for GPU, graphics, processor, AI accelerator, DSP, or high-performance SoC subsystems. Strong hands-on experience with SystemVerilog, Verilog, VHDL, C/C++, and scripting languages such as Python, Perl, Tcl, or shell. Proven experience designing complex RTL blocks with strong understanding of timing, area, power, clocking, reset, CDC/RDC, low-power design, and synthesis constraints. Solid understanding of computer architecture, GPU architecture, processor pipelines, parallel execution models, memory hierarchy, interconnects, and performance/power trade-offs. Experience with RTL quality flows including lint, CDC, reset analysis, synthesis, formal checks, assertions, waveform debug, and regression debug. Ability to work effectively with architecture, verification, physical design, software, compiler, performance, and post-silicon teams. Preferred Skills Deep knowledge of GPU shader architectures, including SIMT/SIMD execution, instruction issue, register files, operand collection, execution pipelines, and latency hiding. Hands-on experience with one or more shader subsystem areas: pipeline design, instruction fetch/decode/dispatch/issue, register file banking, or dependency tracking. Experience with GPU graphics and compute workloads such as vertex, pixel/fragment, compute, mesh, geometry, tessellation, ray tracing, or AI/ML shaders. Knowledge of GPU ISA, shader compiler interaction, instruction scheduling, register allocation, occupancy, and compiler-hardware co-optimization. Experience with mobile GPU design, tile-based rendering, unified shader architectures, and low-power design. Please reach out to [email protected] for more details or to express interest in the role.
